 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| COMLINKTM SERIES CY2CC910 1:10 Clock Fanout Buffer Features * Low-voltage operation * Full-range support: -- 3.3V -- 2.5V * * * * * * * * -- 1.8V Over voltage tolerant input hot swappable 1:10 fanout Drives either a 50-Ohm or 75-Ohm load Low-input capacitance Low-output skew Low-propagation delay Typical (tpd < 4 ns) High-speed operation: -- -200 MHz@1.8V -- 650 MHz@2.5V/3.3V * Industrial versions available * Available packages include: SOIC, SSOP Description The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC910 fanout buffer features one input and ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V Designed for Data Communications clock management applications, the large fanout from a single input reduces loading on the input clock. Cypress employs unique AVCMOS type outputs VOITM (Variable Output Impedance) that dynamically adjust for variable impedance matching and eliminate the need for series damping resistors and reduce noise overall. Block Diagram 3 Pin Configuration Q1 IN 5 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) GND Q1 VDD Q2 GND Q3 VDD Q4 GND VDD 4 ,8 1 5 ,2 0 IN 1 7 9 11 INPUT (AVCMOS) 2 ,6 ,1 0 1 3 ,1 7 12 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 14 20 pin SOIC/SSOP GND 16 18 19 Pin Description Pin Number 1 2,6,10,13,17 4,8,15,20 3,5,7,9,11,12,14,16,18,19 Cypress Semiconductor Corporation Document #: 38-07348 Rev. *A IN Pin Name Input Ground Power Supply Output * CA 95134 * 408-943-2600 Revised October 3, 2002 Description GND VDD Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 * 3901 North First Street * San Jose CY2CC910 COMLINKTM SERIES CY2CC910 Maximum Ratings[1] Storage Temperature: .................................-65C to +150C Ambient Temperature:................................... -40C to +85C Supply Voltage to Ground Potential VCC .................................................................. -0.5V to 4.6V Input ................................................................. -0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................... -0.5V to VDD + 1V DC Output Voltage.................................... -0.5V to VDD + 1V Power Dissipation........................................................ 0.75W Variable Output Impedance Control (VOITM) Pull Down 3.5 Pull Up 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 Iol (A) Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V Vdd = 3.3 V Ioh (A) Vdd = 2.5 V Vdd = 1.8 V Figure 1. Output Voltage vs. Output Current ( TA = 25C) DC Electrical Characteristics @ 3.3V (see Figure 2) Parameter Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 -0.7 VIN = 2.7V VIN = 0.5V IOH = -12 mA IOL = 12 mA 2 Min. 2.3 Typ. 3.3 0.2 0.5 5.8 0.8 1 -1 20 -1.2 -50 100 Max. Unit V V V V uA uA uA V mA uA mV VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07348 Rev. *A Page 2 of 8 COMLINKTM SERIES CY2CC910 DC Electrical Characteristics @ 2.5V (see Figure 2) Parameter Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power Down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 -0.7 VIN = 2.4V VIN = 0.5V IOH = -7 mA IOH= 12 mA IOL = 12 mA 1.6 Min. 1.8 1.6 0.65 5.0 0.8 1 -1 20 -1.2 -50 100 Typ. Max. Unit V V V V V uA uA uA V mA uA mV VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH DC Electrical Characteristics @ 1.8V (see Figure 6) Parameter VDD VIH VIL VOH VOL Description Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = -2 mA IOH = 2 mA Test Condition[2] Min. 1.71 0.65VDD[1.1] -0.3 VDD - 0.45[1.2] 0.45 Max. 1.89 4.3 0.35 VDD[0.6] Unit V V V V V Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Typ. 2.5 6.5 Max. Unit pF pF Power Supply Characteristics (see Figure 2) Parameter ICC ICCD Description Delta ICC Quiescent Power Supply Current Dynamic Power Supply Current Total Power Supply Current Test Conditions (IDD @ VDD = Max and VIN = VDD) - (IDD @ VDD = Max and VIN = VDD - 0.6V) VDD = Max Input toggling 50% Duty Cycle, Outputs Open VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Min. Typ Max 50 0.63 Unit uA mA/ MHz mA IC 25 Note: 2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. Document #: 38-07348 Rev. *A Page 3 of 8 COMLINKTM SERIES CY2CC910 High Frequency Parametrics Parameter DJ Description Jitter, Deterministic Test Conditions 50% duty cycle tW(50-50) The "point to point load circuit" | Output Jitter - Input Jitter | 50% duty cycle tW(50-50) Standard Load Circuit. 50% duty cycle tW(50-50) The "point to point load circuit" Fmax 2.5V Fmax 1.8V Fmax(20) Maximum frequency VDD = 2.5 V Maximum frequency VDD = 1.8V Maximum frequency VDD = 3.3 V Minimum pulse VDD = 3.3 V Minimum pulse VDD = 2.5 V Minimum pulse VDD = 1.8V See Figure 4 Min. Typ. Max. 20 Unit ps Fmax 3.3V Maximum frequency VDD = 3.3V See Figure 2 See Figure 4 160 650 200 200 250 MHz The "point to point load circuit" See Figure 4 VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The "6-pF load circuit" VIN = 1.7/0.0V VOUT = 1.2V/0.4V See Figure 6 MHz MHz MHz 20% duty cycle tW(20-80) See Figure 5 The "point to point load circuit" VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The "point to point load circuit" VIN = 3.0V/0.0V F= 100 MHz VOUT = 2.0V/0.8V The "point to point load circuit" VIN = 2.4V/0.0V F= 100 MHz VOUT = 1.7V/0.7V See Figure 4 1 tW 3.3V tW 2.5V tW 1.8V ns See Figure 4 1 The "6-pF load circuit" See Figure 6 VIN = 1.7V/0.0V VOUT = 1.2V/0.4V 1 AC Switching Characteristics @ 3.3V VDD = 3.3V 5%, Temperature = -40C to +85C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase). Pulse Skew: Skew between opposite transitions of the same output (tPHL - tPLH). See Figure 10 See Figure 9 Description See Figure 3 Min. 1.5 1.5 Typ. 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max. 3.5 3.5 Unit nS nS V/nS V/nS nS nS nS Package Skew: Skew b.etween outputs of different packages at See Figure 11 the same power supply voltage, temperature and package type. AC Switching Characteristics @ 2.5V VDD = 2.5V 5%, Temperature = -40C to +85C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase). See Figure 10 Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9 - tPLH). Package Skew: Skew between outputs of different packages at the same See Figure 11 power supply voltage, temperature and package type. Description See Figure 3 Min. Typ. Max. Unit 1.5 1.5 2.7 2.7 0.8 0.8 0.2 0.2 0.4 3.5 3.5 nS nS V/nS V/nS nS nS nS Document #: 38-07348 Rev. *A Page 4 of 8 COMLINKTM SERIES CY2CC910 AC Switching Characteristics @ 1.8V VDD = 1.8V 5%, Temperature = -40C to +85C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Description Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time 20 - 80% Output Fall Time 20 - 80% Output Skew: Skew between outputs of the same package (in phase). Pulse Skew: Skew between opposite transitions of the same output (tPHL - tPLH). Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Min. Typ. Max. Unit 1.5 2.7 3.5 nS 1.5 2.7 3.5 nS 0.2 1.5 nS 0.2 1.5 nS See Figure 10 0.2 nS See Figure 9 0.2 nS See Figure 7 See Figure 11 0.4 nS Parameter Measurement Information: VDD@3.3V-2.5V From Output Under Test CL = 50 pF 500 ohm From Output Under Test CL = 3 pF 500 ohm Figure 2. Load Circuit [3,4,5] 0.8VDD VDD/2 VDD/2 Figure 4. Point to Point Load Circuit[3,4,5] tw(50-50) Input VDD/2 VDD/2 0V 0.8VDD Input tPLH Output VDD/2 0V tPHL VDD/2 VOH VOL Input tw(20-80) VDD/2 0.8VDD Figure 3. Voltage Waveforms Propagation Delay Times[6] 0V Figure 5. Voltage Waveforms-Pulse Duration[4] Parameter Measurement Information: VDD@1.8V From Output Under Test CL = 6 pF 500 ohm Input tw(50-50) 0.9V 0.9V 0V tw(20-80) 1.8V 0.9V 0V 1.8V Figure 6. Load Circuit [3,4,5] 1.8V 0.9V 0.9V Input Figure 8. Voltage Waveforms-Pulse Duration[4] Input tPLH 0.9V 0V tPHL 0.9V VOH VOL Output Figure 7. Voltage Waveforms Propagation Delay Times[6] Notes: 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50, tR < 2.5 nS, tF < 2.5 nS. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd. Document #: 38-07348 Rev. *A Page 5 of 8 COMLINKTM SERIES CY2CC910 3V 1.5V INPUT tPLH tPHL 0V VOH 1.5V OUTPUT tsk (P) = VOL l tPHL - tPLH l 3V 1.5V Figure 9. Pulse Skew-tsk(p) INPUT tPLH1 tPHL1 0V VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V OUTPUT 2 VOL tPLH 2 tPLH 2 tsk (P) = l tPLH 2 - t PLH1 l or tPHL2 - t PH L1 l 3V 1.5V Figure 10. Output Skew-tsk(0) INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tPLH 2 tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 11. Package Skew - tsk(t) Ordering Information Part Number CY2CC910SI CY2CC910SIT CY2CC910OI CY2CC910OIT CY2CC910SC Package Type 20-pin SOIC 20-pin SOIC-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SOIC Product Flow Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0C to 70C Document #: 38-07348 Rev. *A Page 6 of 8 COMLINKTM SERIES CY2CC910 Ordering Information (continued) CY2CC910SCT CY2CC910OC CY2CC910OCT 20-pin SOIC-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Package Drawing and Dimensions 20-lead (300-mil) Molded SOIC S5 51-85024-A 20-pin Shrunk Small Outline Package O20 51-85077-*C VOI is trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07348 Rev. *A Page 7 of 8 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINKTM SERIES CY2CC910 Document History Page Document Title: CY2CC910 COMLINKTM SERIES 1:10 Clock Fanout Buffer Document #: 38-07348 REV. ** *A ECN NO. 114318 119148 Issue Date 05/10/02 10/07/02 Orig. of Change TSM RGL New Data Sheet Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table. Description of Change Document #: 38-07348 Rev. *A Page 8 of 8 |
Price & Availability of CY2CC910SIT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |